Technical Lead I - VLSI

DV-IP/Subsystems/PCIE/ SoC level verification. GPIO, Sensor and CPU core verification, DDR and USB verification, Power Management Team and GLS simulations, . BUS Interconnect verification of SOC, IP Verification with "C" Based Verification, DV(PCIe, UCIe, Ethernet, USB)PMBUs, APB, I2c, SPI