Associate III - VLSI

JD- Design Verification 3-5 years of experience in Design Verification. Strong expertise in SystemVerilog and UVM. Experience with assertion-based verification. Strong understanding of digital design concepts and computer architecture. Experience in creating verification plans and coverage-driven verification. Hands-on experience with industry-standard simulators such as VCS, Xcelium, or QuestaSim. Experience in debugging complex SoC/IP issues. Knowledge of scripting languages such as Python, Perl, or Shell. Perform block-level and system-level verification. Debug RTL, testbench, and simulation failures.