Associate III - VLSI

Job Summary We are seeking a highly motivated Physical Design Engineer to join our ASIC/VLSI design team. The candidate will be responsible for executing and optimizing the complete physical design flow from synthesis to GDSII signoff for advanced technology nodes. The role requires expertise in timing closure, floorplanning, place-and-route, physical verification, and power optimization using industry-standard EDA tools. Key Responsibilities Perform full-chip and block-level physical design implementation from netlist to GDSII. Develop and execute floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization. Drive timing closure across all design stages and corners. Analyze and resolve setup, hold, signal integrity (SI), IR drop, and electromigration (EM) violations. Perform static timing analysis (STA) and timing signoff. Execute physical verification including DRC, LVS, ERC, and antenna checks. Collaborate with RTL, DFT, STA, power, and verification teams to resolve design issues. Work with foundry signoff requirements and advanced node methodologies. Develop and enhance physical design automation scripts using Tcl, Perl, Python, or Shell. Support tapeout activities and design quality improvement initiatives. Required Skills Technical Skills Strong understanding of VLSI physical design methodologies. Experience with: Floorplanning Power Planning Placement & Optimization CTS Routing & ECO Timing Closure Physical Verification Low Power Design Techniques Good understanding of: Timing concepts and constraints Signal Integrity EM/IR Analysis Multi-mode Multi-corner (MMMC) flows Clock Domain Crossing (CDC) basics DFT awareness EDA Tools Hands-on experience with one or more of: Synopsys Fusion Compiler ICC2 PrimeTime StarRC RedHawk / Voltus Calibre Innovus Tempus Scripting Tcl Perl Python Shell Scripting Qualifications Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related discipline. Strong understanding of semiconductor design flow and tapeout process. Experience with advanced technology nodes (16nm, 7nm, 5nm, 3nm) is an added advantage. Preferred Qualifications Experience in high-performance CPU, GPU, networking, AI/ML accelerator, or automotive SoC designs. Experience in hierarchical or full-chip implementation. Knowledge of UPF/CPF-based low power implementation. Exposure to cloud-based EDA environments and automation frameworks. Key Competencies Strong analytical and problem-solving skills. Ability to work independently and drive closure activities. Effective communication and cross-functional collaboration. Ownership mindset with focus on quality and schedule adherence.