Associate III - VLSI

Job Description: Looking for an experienced RTL Design Engineer with strong hands-on expertise in digital/RTL design and IP integration. The engineer should be capable of independently handling RTL blocks from specification through integration. Mandatory Skills: 6+ years of experience in RTL/Digital Design Hands-on experience in Lint and CDC analysis and closure. Strong experience in IP/subsystem design and integration. Good understanding of AXI/AHB/APB protocols. RTL coding and microarchitecture Hands-on experience with Lint analysis and closure Strong experience in CDC (Clock Domain Crossing) analysis and closure Experience in IP Design and IP/SoC Integration Understanding of Synthesis and STA Good understanding of clock/reset design, FSM, FIFO and synchronization techniques