Lead II - Semiconductor Product Validation

Senior Technical Lead / SME – Platform Hardware (Post Silicon Validation) Summary SME in computer hardware, platform architecture, and system level debug for post silicon validation at semiconductor client and serving as the primary client facing technical owner for complex platform debug programs. Core Impact for Client • Single point of technical ownership for hardware–software interactions, failure triage, and root cause across silicon/firmware/driver. • Builds and scales execution teams with consistent quality, predictability, and dashboard driven visibility with no escalations • Reduces escalations and time to RCA, enabling Key Responsibilities • Leadership & Delivery: Strong people leadership ,Mentoring, performance management and execution discipline. Excellent client communication, solution oriented problem solving and high ownership in dynamic programs. • Client Engagement: Translate milestones into execution plans (resources, tools, lab space, infra), lead reviews/syncs, and proactively manage risks/blockers, reliable delivery of validation milestones. • Debug & RCA: Drive system/kernel level investigations, failure reproduction, crash dump analysis, trace/log capture, and cross domain RCA , Guide fixes with silicon/firmware/driver teams. Talent in WinDBG / KD, JTAG, ITP, TDT, DCI, LTB, kernel installation/KD setup, trace capture; crash dump acquisition and analysis. • Reporting & Governance: Maintain KPI dashboards (schedule, quality, throughput), assure 100% on time delivery, and lead continuous improvement. Technical Expertise (SME) • Platform & Subsystems: Installation/configuration/ deep experience in Windows driver validation and execution in silicon qualification flows. System BIOS/UEFI, USB, Type C, Thunderbolt, DisplayPort, Camera, Storage, Desktop, Power Management, Flash/NAND, Memory Management; strong grasp of PC subsystems architecture. • Protocols & Signals: Working knowledge of USB, PCIe, ability to capture/analyse logic traces and ACPI logs, analyse system (S states) and device (D states).