Design Architect

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence HSV group   is   responsible for   development of the Palladium and Protium   emulation hardware and software   system .  This includes   developing   design and   verification components for complex protocols, to be used for emulation , for e.g.   System   Verilog/Verilog components and SW components written in C/C++ and SV-UVM .  It also requires development of system level RTL   methodologies for   stitching   together   large complex RTL designs in a scalable and   reusable   manner using   and developing advanced tools including those that use AI and ML techniques.

A critical element   with building these SoC models   is performance,   encompassing   performance of the AVIP, the underlying hardware-software design/integration , the   compiler and the   processor-based   Palladium emulator hardware system.

Job Description :

We are seeking a skilled HW and/or   Design Engineering   Architect   to   lead   build ing   representative SoC   sub-systems   using partner systems   (ARM, others)   and Cadence design   and verification   collateral.   The main task is   to build ARM CSS based systems   using Cadence AVIPS and   IP, port   these to   Palladium/Protium hardware and software   and   ensure functional correctness and   make recommendations for   performance   improvements.     Experience with SoC design, verification , ARM bus protocols   and performance analysis is   required .   Familiarity with or interest in developing new methodologies for SoC Integration and Verification Automation is a pl us.

Skills needed :

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