Associate III - VLSI

Job Description: Design Verification Engineer – VLSI/ASIC Job Summary We are looking for a Design Verification Engineer with strong experience in functional verification of complex ASIC/SoC designs. The engineer will be responsible for developing verification environments, creating test plans and test cases, debugging failures, driving functional and code coverage, and ensuring design quality before tape-out. Key Responsibilities Develop and execute ASIC/SoC functional verification strategies and test plans based on design specifications. Develop reusable verification environments using SystemVerilog and UVM. Create testbenches, test cases, sequences, drivers, monitors, scoreboards, assertions, and coverage models. Perform constraint-random and directed verification of RTL designs. Develop and execute regression suites and analyze regression failures. Perform functional coverage and code coverage analysis, identify verification gaps, and drive coverage closure. Debug RTL and testbench issues using simulation waveforms, logs, assertions, and coverage results. Work closely with RTL designers and architecture teams to understand specifications and identify corner cases. Develop SystemVerilog Assertions (SVA) for protocol and functional checks. Verify standard interfaces/protocols such as AMBA AXI/AHB/APB, PCIe, DDR, USB, Ethernet, I2C, SPI, and UART, depending on the project. Support verification at IP, subsystem, and SoC levels. Participate in verification reviews, bug tracking, and technical discussions. Contribute to verification automation using Python, Perl, Tcl, Shell, or similar scripting languages. Support verification closure and sign-off activities. Required Technical Skills Strong understanding of digital design and verification methodologies. Hands-on experience with SystemVerilog and UVM. Experience developing UVM-based verification environments from scratch or enhancing existing environments. Good knowledge of: Constrained-random verification Functional coverage Code coverage Assertion-based verification Verification planning and coverage closure Strong RTL debugging skills with Verilog/SystemVerilog. Experience with simulators/debug environments such as Synopsys VCS, Cadence Xcelium, Siemens Questa, or equivalent. Experience with waveform/debug tools such as Verdi, SimVision, or Questa Visualizer. Understanding of common ASIC/SoC architectures, clock/reset structures, interrupts, memory interfaces, and bus protocols. Scripting experience with Python/Perl/Tcl/Shell. Familiarity with Linux development environments and version-control systems such as Git. Preferred Skills Experience in SoC-level verification and subsystem integration. Experience with verification IP (VIP). Knowledge of formal verification, low-power verification, or UPF. Exposure to C/C++-based test development or embedded software-driven verification. Experience with gate-level simulation (GLS). Exposure to FPGA prototyping or hardware emulation would be an advantage. Qualifications Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related discipline. Relevant hands-on experience in ASIC/SoC Design Verification. Recruiter Search Keywords Design Verification | DV | ASIC Verification | SoC Verification | SystemVerilog | UVM | SVA | Functional Verification | Constraint Random Verification | Testbench | Coverage Closure | Functional Coverage | Code Coverage | VCS | Xcelium | Questa | Verdi | AXI | AHB | APB | PCIe | DDR | Python | RTL Debug